Flyspray:: M5 Bugs:

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ID	Task Type	Severity	Summary	Status	Due In Version
256	Bug	Critical	. Two busses and a bridge can deadlock if the bridge between them has a full queue	New	2.0
269	Minor Enhancement	High	Need general way to schedule events on object-specific clock edges	New	2.1
323	Bug	High	Clean-up CPU statistics	New
324	Bug	High	Add statistics to bus	New
8	Validation	High	verify average stats	Assigned	2.1
126	Major Feature	High	SPARC ISA support	Assigned	2.1
129	Bug	High	Fix database transaction failure behavior	Assigned	2.1
130	Bug	High	Fix everything but scalar stats in database	Assigned
144	Validation	High	verify smt on new cpu model	New	2.1
203	Bug	High	Cache needs stats/params updates	New	2.0
251	Bug	High	valgrind detects two errors	New
253	Bug	High	The bus object constantly schedules itself for one bus cycle later if it has something on it's retry	New	2.0
258	Bug	High	Make o3 cpu handle Nacked Packets	New	2.0
261	Bug	High	Make bus bridge use 1 line cache for partial block writes	New	2.0
326	Bug	High	glibc reads /proc/meminfo and that can effect simulation	New
337	Bug	High	Checkpoint Tester Identifies Mismatches (Bugs) for X86_FS	Unconfirmed
30	Minor Enhancement	Medium	split up eventq.hh	Unconfirmed	2.1
33	Major Feature	Medium	clean up the m5 #includes	Unconfirmed	2.1
38	Bug	Medium	Add some disk statistics	Unconfirmed	2.1
74	Minor Enhancement	Medium	Reenable support for WH64/fast allocate	Unconfirmed	2.1

Showing tasks 1 - 20 of 102

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